Having complicated circuits and a large number of component parts, a highly accurate analog/digital (A/D) converter requires increases in circuit area and power consumption. In recent years, a delta sigma (ΔΣ) A/D converter achieving high accuracy by an over sampling technique in spite of a small number of component parts has been actively developed, and thus various circuit systems have been studied. Generally a ΔΣ A/D converter feeds back a converted digital output signal to an analog input signal and then modulates frequency characteristics thereby to secure a desired conversion band and accuracy. The ΔΣ A/D converter requires a high speed clock rate dozens of times as high as the converted signal bandwidth, and thereby requires circuits to operate at such a high speed. In this regard, such high speed circuits have been put in practical use thanks to speed-up of MOS transistors.
A configuration example of a ΔΣ A/D converter is disclosed in FIG. 1 of Patent Literature 1. In the ΔΣ A/D converter, a quantizer is connected to an output of a filter circuit constituted of multiple integration circuits. An output signal of the quantizer is outputted via an encoder and is also fed back to the filter circuit via a D/A converter.
Here, the ΔΣ A/D converter disclosed in Patent Literature 1 is a discrete-time type. Meanwhile, attention has been attracted to a continuous-time type which achieves lower power consumption than the discrete-time type, and which is also suitable for a high-speed high-frequency signal. The continuous-time ΔΣ A/D converter is configured based on the assumption that an excess loop delay (ELD) from the sampling of the output signal of the quantizer until the feedback of the signal to the filter circuit is almost zero. However, when the sampling clock rate is high, the ELD can be no longer ignored.
A configuration in which the ELD is compensated is disclosed in FIG. 2 of Non-patent Literature 1. FIG. 6 attached hereto is a block diagram of a continuous-time ΔΣ A/D converter disclosed in FIG. 2 of Non-patent Literature 1. The continuous-time ΔΣ A/D converter includes adder circuits 1 to 3, integration circuits 4 to 6, voltage-current conversion circuits K4 to K7 and Kz, an internal A/D converter (ADC), two D/A converters (DACs) -A and -B, and two D-latches (D-LATCHes).
In the continuous-time ΔΣ converter, an analog input signal IN and output signals of the integration circuits 4 to 6 are converted into current signals by the voltage-current conversion circuits K4 to K7, respectively, and the currents are added in the adder circuit 3 positioned at a prior stage of the internal ADC. In other words, this continuous-time ΔΣ converter is a feedforward type.
The internal ADC, which is a quantizer, converts an output signal of the adder circuit 3 into a 5-bit digital value and outputs a digital output signal OUT. The DAC-A feed backs an analog current in response to the digital output signal OUT to the adder circuit 1. In addition, the DAC-B feed backs an analog current in response to the digital output signal OUT to the adder circuit 3. Thereby, delay compensation of the internal ADC is performed.
Here, a delay time of the output signal OUT of the internal A/D converter ADC largely fluctuates due to the amplitude or the like of a signal inputted from the adder circuit 3. In order to reduce the amount of fluctuation, the output signal OUT of the internal ADC is fed back to the DAC-A via the two D-LATCHes.
Meanwhile, the feedback from the output signal OUT to the input signal IN is constantly delayed by one clock cycle, and the feedback is not performed during a period from a sampling timing to the next sampling timing. The DAC-B is provided to compensate this problem. The DAC-B receives the output signal OUT only a half clock cycle earlier than the DAC-A, and performs feedback to the adder circuit 3 immediately before the internal ADC.
Unlike the signal from the DAC-A, the signal from the DAC-B is not inputted to the integration circuits 3 to 6. Thus, the influence of the feedback by the DAC-B is limited in the period from the sampling timing to the next sampling timing at which the feedback of the DAC-A is not performed. Accordingly, even when the DAC-A and DAC-B are used in a combination, the system operates without any problem. Here, the feedback coefficient of the DAC-B can be calculated by using an impulse response equalization method.
[Citation List]
[Patent Literatures]
    [Patent Literature 1] Japanese Patent Application Publication No. 2006-41992    [Non-patent Literature 1] Yan, S. and one other, “A continuous-time ΣΔ modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth,” IEEE Journal of Solid-State Circuits, January 2004, Vol. 39, No. 1, p. 75-86